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document number: MPC18730 rev. 4.0, 8/2006 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2006. all rights reserved. power management ic with five regulated outputs programmed through 3-wire serial interface the MPC18730 power management ic (pmic) regulates five independent output voltages from either a single cell li-ion (2.7 v to 4.2 v input range) or from a single cell ni-mh or dry cell (0.9 v to 2.2 v input range). the pmic includes 2 dc-dc converters and 3 low drop out (ldo) linear regulators. the output voltage for each of the 5 output voltages is set independently through a 3-wir e serial interface. the serial interface also configures the pmic's versatile start-up control system, which includes multiple wakeup, sleep, standby, and reset modes to minimize power consumption for portable equipment. in single cell li-ion applications two dc-dc converters are configured as buck (step-down) regulat ors. in single cell ni-mh or dry cell applications, one dc-dc converter is configured as a boost (step-up) regulator, and the ot her as buck-boost regulator. the dc- dc converters' output voltages have set ranges 1.613 v to 3.2 v at up to 120 ma, and 0.805 v to 1.5 v up to 100 ma. features ? operates from single cell li-ion, ni-mh, or alkaline ? 2 dc-dc converters ? 3 low drop regulators ? serial interface sets output voltages ? 4 wake inputs ? low current standby mode ? pb-free packaging designated by suffix code ep figure 1. MPC18730 simplified application diagram power management ic ep suffix (pb-free) 98arl10571d 64-pin qfn 18730 ordering information device temperature range (t a ) package MPC18730ep/r2 -10c to 65c 64 qfn MPC18730 vbatt vref vb vo pgood1 control logic inputs gnd gndgate vout1 sw1 vout2 vo2_sense sw2 srego1 srego2 srego3 vgate swgate vb sregi1 sregi2 sregi3 vgate_ext 1.613 v to 3.2 v 0.865 v to 2.8 v 0.011 v to 2.8 v 2.08 v to 2.8 v programmable 0.805 v to 1.5 v programmable programmable programmable programmable mcu pgood2 vo { vo1_sense
analog integrated circuit device data 2 freescale semiconductor 18730 internal block diagram internal block diagram figure 2. MPC18730 simplified internal block diagram vgate_ext vref eain1 eaout1 dmax1 pgnd1 vin1 vout1 sw2 v_stdby lvb hvb eaout2 eain2 dmax2 pgood2_delay pgnd2 vin2 vout2 vo2_sense_in data strb vgate srego1 sregc1 sregc2 sregc3 gndgate sregi1 watchdog gnd seq_select ch_pump srego2 srego3 sregi3 clear vo1_sense bandgap vo1_sense vo1_sense vbatt vgate power switch1 lvb pgood1(int) pgood1(int) pgood1(int) driver reference vo1_sense step-updown dc/dc vmode pgood1(int) vref power switch2 ref2 pgood2(int) vgate step-updown dc/dc pgood2(int) control vo1_sense vbatt series pass vgate vgate vbatt vref regulator1 series pass vgate vbatt ref3 ref4 ref5 seq_select ext_clock ref1 ref2 ref3 ref4 ref5 ref dac vmode series pass vgate regulator3 regulator2 cpoff vgate_duty vg_select vgate hg lg sregi2 swgate on ext gate on ext_clock clear sckin wake1b wake2b wake3b wake4b reset1_th pgood1 lswo sleep pgood1_delay buffer sreg2g control logic step-up dc/dc convertor converter reset block 2 vo1_sense reset block 1 pgood2 pgood1(int) ch1 converter ch2 v_stdby (int) vgate pgood2 sregc1 vgatesel1 vgatesel2 vbatt vo2_sense vo1_sense sw1 vgate vo1_sense ref1
analog integrated circuit device data freescale semiconductor 3 18730 pin connections pin connections figure 3. MPC18730 pin connections table 1. MPC18730 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 14 . pin number pin name pin function formal name definition 1 clear input clear start-up signal input latch/clear 2 wake4b input wake signal 4 start-up signal input 4 3 wake3b input wake signal 3 start-up signal input 3 4 wake2b input wake signal 2 start-up signal input 2 5 wake1b input wake signal 1 start-up signal input 1 6 lswo output low-side switch output low-side switch output pin 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 top view clear wake4b wake3b wake2b wake1b lswo lvb hvb v_stdby vo1_sense vout1 vin1 sw1 sw1 pgnd1 pgnd1 pgood1 pgood1_delay eaout1 eain1 ch_pump vgate gndgate vbatt eain2 pgood2_delay pgood2 pgnd2 sw2 sw2 vin2 vout2 vo2_sense_in srego3 sregi3 srego2 vo2_sense srego1 sregi1 sregc1 sregc2 sregc3 gnd sreg2g vgatesel2 lg vref dmax1 hg data strb sckin watchdog 1 49 33 17 18 vgate_ext sregi2 pgnd2 seq_select vgatesel1 dmax2 swgate reset1_th sleep ext_clock eaout2
analog integrated circuit device data 4 freescale semiconductor 18730 pin connections 7 lvb input low voltage battery vb power supply connection for ni_mh 8 hvb input high voltage battery vb power supply connection for li_ion 9 v_stdby output standby voltage v_stdby voltage output 10 vo1_sense input voltage input 1 switching power supply circuit 1, vo1_sense voltage input, vo1_sense power supply 11 vout1 output voltage output 1 power switch 1 output 12 vin1 output voltage output 1 switching power supply circuit 1 output 13 sw1 power switching 1 switching power supply circuit 1 coil connection 14 sw1 power switching 1 switching power supply circuit 1 coil connection 15 pgnd1 ground power ground 1 switching power supply circuit 1 power gnd 16 pgnd1 ground power ground 1 switching power supply circuit 1 power gnd 17 pgood1 output inverted reset output 1 reset circuit 1 reset signal output 18 pgood1_delay input reset delay capacitor 1 reset circuit 1 reset signal delaying capacitor connection 19 reset1_th output reset1 adjustment switching power supply circuit 1 reset voltage reference output 20 dmax1 power duty control switching power supply circuit 1 maximum duty setting 21 eaout1 output reference feedback 1 switching power supply circuit 1 error amp output 22 eain1 input input minus 1 switching power supply circuit 1 error amp inverse input 23 ch_pump power charge pump capacitor vgate power supply circuit charge pump capacitor connection 24 vgate output gate voltage vgate power supply circuit voltage output, pre-diver circuit power supply 25 swgate power switching vgate power supply circuit coil connection 26 gndgate ground power ground 3 vgate power supply circuit power gnd 27 vbatt power battery voltage vb power supply connection 28 vgatesel2 output vgate select 2 vg power supply circuit output voltage setting 2 29 vgatesel1 output vgate select 1 vgate power supply circuit output voltage setting 1 30 eain2 input input minus switching power supply circuit 2 error amp inverting input 31 eaout2 output reference feedback 2 switching power supply circuit 2 error amp output 32 dmax2 power duty control switching power supply circuit 2 maximum duty setting 33 pgood2_delay input reset delay capacitor 1 reset circuit 2 reset signal delay capacitor connection 34 pgood2 output inverted reset output 2 reset circuit 2 reset signal output 35 pgnd2 ground power ground 2 switching power supply circuit 2 power gnd 36 pgnd2 ground power ground 2 switching power supply circuit 2 power gnd table 1. MPC18730 pin definitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 14 . pin number pin name pin function formal name definition
analog integrated circuit device data freescale semiconductor 5 18730 pin connections 37 sw2 power switching switching power supply circuit 2 coil connection 38 sw2 power switching switching power supply circuit 2 coil connection 39 vin2 output voltage output switching power supply circuit 2 output 40 vout2 output voltage output power switch 2 output 41 vo2_sense_in input voltage input power switch 2 voltage input 42 vo2_sense input voltage input switching power supply circuit 2 vo2_sense voltage input 43 hg output step down top fet 2 switching power supply circuit 2 step down top side fet gate output for ni_mh 44 lg output step down bottom fet 2 switching power supply circuit 2 step down bottom side frt gate output for ni_mh 45 vgate_ext output gate switch external transistor gate signal output 46 sregc3 power regulator capacitor 3 series pass power supply circ uit 3 external feedback connection 47 srego3 output regulator output 3 series pass power supply circuit 3 output 48 sregi3 power regulator input 3 series pass power supply circuit 3 power supply 49 sregc2 power regulator capacitor 2 series pass power supply circ uit 2 external feedback connection 50 sreg2g output regulator gate output 2 series pass power supply circuit 2 external transistor gate signal output 51 srego2 output regulator output 2 series pass power supply circuit 2 output 52 sregi2 power regulator input 2 series pass power supply circuit 2 power supply 53 sregc1 power regulator capacitor 1 series pass power supply circ uit 1 external feedback connection 54 srego1 output regulator output 1 series pass power supply circuit 1 output 55 sregi1 power regulator input 1 series pass power supply circuit 1 power supply 56 gnd ground ground gnd 57 vref output reference voltage reference voltage output 58 data input data signal serial interface data signal input 59 strb input strobe serial interface strobe signal input 60 sckin input serial clock serial interface clock signal input 61 watchdog input watch dog timer watchdog timer capacitor connection 62 seq_select input sequence input start-up sequence setting input 63 ext_clock input clock input external synchronous clock signal input 64 sleep input sleep signal sleep signal input table 1. MPC18730 pin definitions (continued) a functional description of each pin can be found in the functional pin description section beginning on page 14 . pin number pin name pin function formal name definition
analog integrated circuit device data 6 freescale semiconductor 18730 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings power supply voltage v batt -0.5 to 5.0 v analog signal input (1) v inan -0.5 to vo1+0.5 v logic signal input wake1~4b clear, sleep, ext_clock, sckin, data, strb vgatesel1,2 v ilrstb v ilgc v ilgsel -0.5 to v_stdby+0.5 -0.5 to vo1_sense+0.5 -0.5 to vbatt+0.5 v output power current vout1 power supply circuit (2) vout2 power supply circuit sreg1 power supply circuit sreg2 power supply circuit sreg3 power supply circuit vgate power supply circuit pgood1 power supply circuit i ovo1 i ovo2 i oreg1 i oreg2 i oreg3 i ovg i opgood1 120 100 80 100 80 8 -20 ma open-drain output apply voltage pgood1 lswo v iodr v iodv -0.5 to 3.3 -0.5 to 3.3 v esd voltage (3) human body model (hbm) machine model (mm) charge device model (cdm) v esd1 v esd2 v cdm 1500 200 750 v thermal ratings operating temperature ambient junction t a t j -10 to 65 150 c storage temperature t stg -50 to 150 c thermal resistance (4) junction to ambient r ja 69 c/w lead soldering temperature (5) t solder 260 c notes 1. vref, dmax1, dmax2, sregc1, sregc2, sregc3 and reset1_th. 2. includes the series pass power supply circuit output current 3. esd testing is performed in accordance with the human body model (hbm) (c zap = 100 pf, r zap = 1500 ? ), the machine model (mm) (c zap = 200 pf, r zap = 0 ? ), and the charge device model (cdm), robotic (c zap = 4.0pf). 4. device mounted on a 2s2p test board, in accordance with jedec jesd51-6 and jesd51-7. 5. pin soldering temperature limit is for 10 seconds maximum dura tion. not designed for immersion so ldering. exceeding these lim its may cause malfunction or permanent damage to the device.
analog integrated circuit device data freescale semiconductor 7 18730 electrical characteristics static static table 3. static electric al characteristics characteristics noted under conditions vbatt = 1.2 v, vo1_sense = 2.4 v, vgate= 6.0 v, f clk = 176.4 khz unless otherwise noted. typical values noted refl ect the approximate par ameter means at t a = 27c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit general vb power supply voltage power supply voltage 1 power supply voltage 2 v lvb v hvb 0.9 2.7 1.2 3.5 2.2 4.2 v series regulator input voltage (6) , (7) v sregi v sreg +0.2 (8) v sreg +0.3 v sreg +0.4 v start-up voltage v bst 0.9 - - v analog signal input (9) v iana 0 - vo1_sense v logic signal input wake1~4b clear, sleep, ext_clock, data, strb and sckin vgatesel1, 2 v ilrstb v ilgc v ilgsel 0 0 0 - - - v_stdby vo1_sense vbatt v output power current vout1 power supply circuit (10) vout2 power supply circuit (10) sreg1 power supply circuit sreg2 power supply circuit sreg3 power supply circuit vgate power supply circuit pgood i ovout1 i ovout2 i osreg1 i osreg2 i osreg3 i ovg i opgood 0 0 5.0 6.0 5.0 -5.0 - - - - - - - - 100 80 60 80 60 6.0 0 ma supply current in stand-by mode vb supply current (vb = 1.2 v for ni_mh) (hvb = 3.5 v for li-ion) i bsni i bsli - - 5.0 8.0 10 12 a supply current in operating mode vb supply current (vb = 1.2 v for ni_mh) (hvb = 3.5 v for li-ion) i bni i bli - - 9.0 7.0 18 14 ma reference power supply circuit output voltage output current v ref i oref 1.255 -0.3 1.275 - 1.295 0.3 v ma switching power supply 1 vout1 output voltage (i o = 0~100 ma) v out1 2.3 2.4 2.5 v notes 6. when applying voltage from an external source. 7. 0.3 v when vgate is 4.5 v. 8. provide 2 v or higher for the voltage difference (vgate - vo1_sense). 9. vref, dmax1, dmax2, sregc1, sregc2, sregc3 and reset1_th. 10. includes the series pass power supply circuit output current.
analog integrated circuit device data 8 freescale semiconductor 18730 electrical characteristics static switching power supply 2 vout2 output voltage (i o = 0~80 ma) hg output voltage (11) (i source = 400 a) (i sink = 400 a) lg output voltage (11) (i source = 400 a) (i sink = 400 a) v out2 v dw2th v dw2tl v dw2bh v dw2bl 1.05 5.2 0 5.2 0 1.15 - - - - 1.25 vgate 0.3 vgate 0.3 v series pass power supply circuit sreg1 control voltage (i o = 5~60 ma) (12) sreg1-error amp input offset voltage (13) sreg2 control voltage (i o = 6~80 ma) (12) sreg2-error amp input offset voltage (14) sreg3 control voltage (i o = 5~60 ma) (12) sreg3-error amp input offset voltage (15) sreg2g output voltage (16) (i source = 2.5 a) (i sink = 2.5 a) v sreg1 sr1ofst v sreg2 sr2ofst v sreg3 sr3ofst sreg2gh sreg2gl 2.7 -13.5 2.7 -17 2.7 -11 5.0 0 2.8 - 2.8 - 2.8 - - - 2.9 24.5 2.9 17 2.9 23 vgate 0.5 v mv v mv v mv v v power switch on resistance vout1 circuit vout2 circuit r vout1 r vout2 - - 0.4 0.4 0.6 0.6 w vgate power supply circuit (i o = 0~6 ma) (17) (i o = 0~6 ma) (18) ch_pump output voltage (i source = 2.5 ma) (i sink = 2.5 ma) vgh voltage (certified value) v gate_00 v gate_10 v o1_sense1lh v o1_sense_1ll v gh 5.5 4.6 vb x 0.85 0 - 6.0 5.0 - - - 6.5 5.4 vb 0.4 10.5 v v_stdby output voltage for li_ion (i o = 300 a) (19) v lvb 1.75 - 2.45 v notes 11. connect a transistor with gate capacity of 200 pf or smaller to hg and lg 12. if a capacitor with capacitance of 22 f is connected to srego, use a phase compensation capacitor between srego and sregc when the load is 5 ma (6 ma for sreg2) or lower. the output vo ltage values shown in the table as sume that external resistance i s connected as follows: sregi1 = 3.0 v to 3.3 v, 65.14k ? between srego1 and sregc1, 34.86k ? between sregc1 and gnd. sregi2 = 3.0 v to 3.3 v, 54.46k ? between srego2 and sregc2, 45.54k ? between sregc2 and gnd. sregi3 = 3.0 v to 3.3 v, 73.84k ? between srego3 and sregc3, 26.16k ? between sregc3 and gnd. 13. calculated by the right formula for inpu t offset: sr1ofst = (vref x 0.77) - (srego1 (100k 34.86k)) 14. calculated by the right formula for inpu t offset: sr2ofst = (vref x 1) - (srego1 (100k 45.54k)) 15. calculated by the right formula for inpu t offset: sr3ofst = (vref x 0.58) - (srego1 (100k 26.16k)) 16. connect a transistor with gate capacity of 300 pf or smaller to reg2g. 17. when vgatesel1 is low and vgatesel2 is low, i/o = 3 ma or higher is certified by specification. 18. when vgatesel1 is high and vgatesel2 is low, i/o = 3 ma or higher is certified by specification. 19. when hvb is 4.2 v and the load from v_stdby is 0.5 a or higher. table 3. static electrical characteristics (continued) characteristics noted under conditions vbatt = 1.2 v, vo1_sense = 2.4 v, vgate= 6.0 v, f clk = 176.4 khz unless otherwise noted. typical values noted refl ect the approximate par ameter means at t a = 27c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 9 18730 electrical characteristics static reset circuit reset voltage 1 reset voltage 2 hysteresis voltage 1 (@rst1) hysteresis voltage 2 (@rst2) pgood (v pgood = 2.4 v) (i sink = 2 ma) pgood_delay (i sink = 100 a) high level threshold voltage low level threshold voltage pgood_delay pull-up resistance v rst1 v rst2 v hyrs1 v hyrs2 i pgood1,2 v pgood1,2 v olcr1,2 v ihcr1,2 v ilcr1,2 r puprc1,2 0.85 x vo1_sense 0.80 x vo1_sense 40 50 0 0 0 1.25 0.75 50 0.88 x vo1_sense 0.85 x vo1_sense 78 75 - - - 1.42 1.00 100 0.91 x vo1_sense 0.90 x vo1_sense 115 100 10 0.5 0.7 1.65 1.15 150 v v mv mv a v v v v k ? v_stdby output resistance output resistance (vo1_sense) output resistance (vbatt) r vo1_sense r vb - - 30 200 45 400 w lswo output resistance output resistance r lswo - 42 50 w vgate_ext vgate_ext output voltage (i source = 100 a) (i sink = 100 a) v ohextg v olextg vgate x 0.9 0 - - vgate vgate x 0.1 v logic input "h" level input voltage (20) "l" level input voltage (20) "h" level input voltage (21) "l" level input voltage (21) "h" level input voltage (22) "l" level input voltage (22) "h" level input current (20) , (22) "l" level input current (22) , (23) pull up resistance (24) pull down resistance (25) v ihvs v ilvs v ih v il v ihvb v ilvb i ih i il r pup r pdw v_stdby - 0.2 - 1.5 - vb - 0.2 - -1.0 -1.0 410 330 - - - - - - - - 590 480 - 0.2 - 0.4 - 0.2 1.0 1.0 770 625 v v v v v v a a k ? k ? notes 20. applied to wakeb1 ~ 4 and seq_select. 21. applied to clear, sleep, ext_clock, data, strb and sckin. 22. applied to vgatesel1 and 2. 23. applied to wakeb1 ~ 3, clear, sleep, ext_clock, data, strb, sckin and seq_select. 24. applied to wakeb4. 25. applied to clear, sleep, ext_clock, data, strb and sckin. table 3. static electrical characteristics (continued) characteristics noted under conditions vbatt = 1.2 v, vo1_sense = 2.4 v, vgate= 6.0 v, f clk = 176.4 khz unless otherwise noted. typical values noted refl ect the approximate par ameter means at t a = 27c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 10 freescale semiconductor 18730 electrical characteristics dynamic dynamic table 4. dynamic electri cal characteristics characteristics noted under conditions vbatt = 1.2 v, vo1_sense = 2.4 v, vgate = 6.0 v, f clk = 176.4 khz unless otherwise noted. typical values noted refl ect the approximate par ameter means at t a = 27c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit oscillator internal oscillation frequency f ick 150 200 250 khz micro controller interface clock signal input (26) f clk - 176.4 - khz serial interface (refer to figure 5, serial interface timing diagrams ) data set up time data hold time sckin clock frequency sckin 'h' pulse width sckin 'l' pulse width sckin hold time strb set up time strb pulse width t s t h f sck t wckh t wckl t hck t ssb t wsb 20 20 - 50 50 50 50 50 - - 6.0 - - - - - - - - - - - - - nsec nsec mhz nsec nsec nsec nsec nsec notes 26. duty 50%.
analog integrated circuit device data freescale semiconductor 11 18730 electrical characteristics timing diagrams timing diagrams figure 4. power supply start-up timing diagram wake1~4(int) ext_clock v_stdby vbatt vgate pgood1(int) pgood1 vo1_sense vout1 vo2_sense vout2 sreg1~3 data strb clear sleep vbatt vbatt vbatt vo1_sense vgate vbatt vo1_sense vo2_sense vbatt vbatt int ext vo1_sense vo1_sense vo2_sense data pgood1 vo1_sense pgood2(int) standby mode *1: when using ni_mh. high-z when using li_ion. start-up (serial setting) pgood_delay set value pgood_delay set value seq_select setting seq_select setting operation mode standby mode vo1_sense vo1_sense vbatt
analog integrated circuit device data 12 freescale semiconductor 18730 electrical characteristics timing diagrams figure 5. serial interface timing diagrams twelve bits immediately before start-up of strb are always effective. upon power on, the internal power on reset works to initialize the registers. serial data is fetched in the order of add_[3], add_[2], ..., add_[0], data1_[3], data1_[2], ...., data2_[0]. table 5. serial interface functions register name address data1 data2 0 clear, sleep 1000 clear sleep reserved reserved reserved reserved reserved reserved 1 power mode 0001 psw1 psw2 pgood1 vout2 sreg1 sreg2 sreg3 pgood2 2 clock select 0010 ext / int half freq rstb sleep s_off_vgate vg_duty[3] vg_duty[2] vg_duty[1] vg_duty[0] 3 vo1_sense 0011 msb vo1_sense output voltage lsb s_off_vo1_sense 4 vo2_sense 0100 msb vo2_sense output voltage lsb s_off_vo2_sense 5 sreg1 0101 msb sreg1 output voltage lsb reserved 6 sreg2 0110 msb sreg2 output voltage lsb 7 sreg3 0111 msb sreg3 output voltage lsb cp off extg on sckin data strb t s t h t ssb t wckh t wckl t hck a3 d0 t wsb a2 table 6. block operation input output wake (int) pgood1 (int) pgood1 pgood2(int) seq_select vgate vo1_sense vo2_sense vout1,2 reg 1,2,3 l x x x x - - - - - h l l l l o o - - - h h l l l o o - - o h h l l h o o - - - h h h h l o o o o o h h h h h o o o o o o : operation, - : stop, x : don?t care
analog integrated circuit device data freescale semiconductor 13 18730 electrical characteristics timing diagrams table 7. start-up sequence settings seq_sele ct clear/ sleep series regulators v_stdby pgood2(ext) pgood2(int) gnd pgood1(ext) pgood1(int)
analog integrated circuit device data 14 freescale semiconductor 18730 functional description introduction functional description introduction the 18730 power management int egrated circuit provides five independent output voltages for the micro controller from either a single cell li-ion or from a single cell ni-mh or dry cell. the pmic includes two dc to dc converters and three low drop out linear regulators. the output voltage for each of the five output voltages is set independently through a 3-wire serial interface. the pmic has multiple wakeup, sleep, and reset modes to minimize power consumption for portable equipment. in single cell li-ion applications two dc-dc converters are configured as buck regulators. in single cell ni-mh or dry cell applications, one dc-dc converter is configured as a boost regulator, and the other as buck-boost regulator. functional pin description clear pin (clear) this clear input signal makes clear internal latches for wake signal holding. the w ake control circuit can not receive another wake input until the latch is cleared by this clear input. wake signal pins (wake1b, wake2b, wake3b, wake4b) ... active low any one wake input signal of these four wake inputs awakes this device from sl eep mode. the wake signals can be made with external low side mechanical switch and resistance that is pulled up to vstb rail. low-side switch output pin (lswo) low-side switch output that is turned on with ?clear? signal. it can be used for external key input latches clear. low voltage battery pin (lvb) this input pin is used for temporarily power supply while wake up for 1cell ni-mh battery or 1 cell dry cell battery (= low voltage battery) use. it has to be connected to vb rail. when li-ion battery is used, the pin has to be open. high voltage battery pin (hvb) this input pin is used for temporarily power supply while wake up for li-ion battery (= high voltage battery) use. it has to be connected to the vb rail. when a ni-mh battery is used, the pin has to be connected to ground level. standby voltage pin (v_stdby) standby voltage is made from lvb or hvb that depends on which battery is used. this voltage is used for internal logic and analog circuit at standby (sleep) mode temporarily before ?vo1_sense? voltage is established. voltage input pins (vo1_sense, vo2_sense) this power supply input pin named ?vo1_sens or vo2_sense? is for internal logic and analog circuits and for input of ?vout1? output via po wer switch. input for ?vout2? is ?vo2_sense_in? pin. it is supplied from the output of channel-1 or channel-2 dc/dc converter as ?vo1_senseor vo2_sense. voltage output pins (vout1, vout2) output ?vo1_sense or ?vo2_sense? voltage controlled internal power switch. power input pins (vin1, vin2) the power input pins (vin1, vin2) are drain pins on the top side fet of the dc/dc conv erter switcher. they are the power input for the buck converter and output for the boost converter. switching pins (sw1, sw2) switching pins (sw1, sw2) ar e the output of the half bridge and connect to the external inductance. power ground pins (pgnd1, pgnd2, gndgate) ground level node for dc/dc converter and charge pump portion. inverted reset output pins (pgood1, pgood2) reset signal output for external mpu or the something controller. pgood1 keeps ?low? level while the vo1_sense voltage is less than internal reference voltage. pgood2 follows to vo2_sense voltage. reset delay capacitor pins (pgood1_delay, pgood2_delay) the capacitor connected to this pin decides delay time to negate the reset signal from exceeding the reference voltage level. reset 1 adjustment pin (reset1_th) used to adjust the reset level with external resistance which is connected to vo1_sense for pgood1.
analog integrated circuit device data freescale semiconductor 15 18730 functional description functional pin description duty control pins (dmax1, dmax2) connected external voltage to this pin via capacitance can control the duty of dc/dc converte r switching. use of the pin for this is not recommended. reference feedback pins (eaout1, eaout2) output node of internal error amp. for dc/dc converter 1 and 2. used for phase compensation. input minus pins (eain1, eain2) minus input of internal error amp. for dc/dc converter 1 and 2. used for phase compensation. charge pump capacitor pin (ch_pump) in case of use higher voltage than vgate externally, connect capacitance and di odes between vgate. the charge pump structure can output vgate + vb - 2 x vf voltage. there is no meaning for ni-mh or dry cell battery, because the vb voltage is almost same as 2 x vf voltage. recommend to use for li-ion battery use. gate voltage pin (vgate) output pin of boost converte r for gate drive voltage. the output voltage is decided by vgsel input. switching for gate voltage pin (swgate) switching pin for vgate boost converter. connect to external inductance. battery voltage pin (vbatt) power supply input that connects to ni-mh or dry cell or li-ion battery. vgate select pins (vgatesel1, vgatesel2) vgate output voltage is decided with these two bits input. voltage input for power switch 2 pin (vo2_sense_in) input of vout2 output via power switch. connect to vo2_sense pin externally. step down fet gate drive pins (hg, lg) gate drive output pins for external fets to use dc/dc converter 2 as buck / boost converter. gate switch pin (vgate_ext) gate drive output pin for external low side switch. it can be used for power switch turnin g on/off for remote controller part. regulator control pins (sregc1, sregc2, sregc3) feed back pin for each series regulators. this pin voltage is compared with internal reference voltage. input the feed back voltage that divided srego voltage by resistances. regulator output pins (srego1, srego2, srego3) series regulator output pins. all output voltages can be variable with internal dac via serial i/f. regulator input pins (sregi1, sregi2, sregi3) series regulator power input pins. to be connected to battery voltage in general. ground pin (gnd) ground pin for logic and analog circuit portion (not power portion). recommend to connect to clean ground which separated with power ground line. reference voltage pin (vref) output of internal reference voltage. it can be used externally. output current capacity is less than 300 a. data input pin (data) serial data input pin for the serial interface. the last 12 bits received before the strobe signal?s low to high transition are latched. strobe pin (strb) strobe signal input pin for serial interface. it latches the 12 bits of data input to the internal control registers. serial clock pin (sckin) clock input pin for serial interface. input data are taken in to i/f with this clock. watch dog timer pin (watchdog) watch dog timer prevent unstable wake up (flips between wake-up and failure). if there is no ?clear? input after any wakenb input before this wa tchdog is expired, this device moves to ?sleep? mode to prevent wake failure hanging-up situation. sequence select pi n (seq_select) select judgement reset channel for wake-up complete with this input. if this input level is v_stdby voltage, this device judges the wake-up completion with reset2 (dc/ dc2). if it is ground, jud ge with reset1 (dc/dc1). see table 7, on page 13 .
analog integrated circuit device data 16 freescale semiconductor 18730 functional description functional pin description clock input pin (ext_clock) clock input pin for internal switching part. this device has a oscillator internally, but can use this input clock for internal switching frequency. it is select ed by clock select bit. see table 19, on page 25 . sleep mode pin (sleep) the sleep input signal puts the device in sleep mode. all output voltages are down, and internal current consumption will be minimum.
analog integrated circuit device data freescale semiconductor 17 18730 functional device operation operational modes functional device operation operational modes start-up control inpu t (system control) the latch is set at the rising edge of any w ake1b-4b input pin, and wake(int) goes high. wake1~4b inputs consist of or logic. at this time, the input pin which went low keeps latched until clear goes high. after the latch is reset by clear, wake(int) goes low when sleep goes high. the latch is also cleared and wake(int) goes low when sleep goes high before the latch is cleared by clear. in this case, clear keeps negated while pgood1, 2(ext) is low. sleep keeps negated while p good1, 2(ext) is low or clear is high. the period of time for which clear and sleep are negated can be set by the seq_select pin. refer to truth table 5, on page 12 for the correspondence between the seq_select pin settings and negation period. if sleep goes high to place the chip into the standby mode while any of the wakeb pi ns is low, the chip can be awakened again. this may happen if, when an wakeb pin and lswo are connected, sleep goes high earlier than the period of time (*1) specified by the external component of the wakeb pin. also, if the period of time a fter wake(int) goes high until clear goes high from low is longer than the time specified by watchdog, internal sleep wil l start up to place the chip into the standby mode. (*1: it is 30 sec when a capac itor is not connected as the external component.) figure 6. start-up timing diagram standby power supply circuit figure 7. standby power supply circuit diagram when pgood1(int) is low, output lvb voltage to v_stdby pin. when pgood1 (int) is high, output vo1_sense voltage to v_std by pin. when clear is low, lswo is open. when pgood1(int) is high and clear is high, lswo output voltage turns gnd. when pgood1(int) is low and pgood1 is high, discharge the external clear watchdog wakeb wake(int) time specified by watchdog vbatt clear lvb vbatt short-circuit vbatt and lvb, and connect a schottky diode between vbatt and v_stdby only when using ni_mh. when using li_ion, leave lvb open, and short- circuit hvb and vbatt. pgood1 pgood1(int) vo1_sense lswo v_stdby v_stdby hvb standby power supply control
analog integrated circuit device data 18 freescale semiconductor 18730 functional device operation operational modes capacitor which is connected to v_stdby. when using ni_mh, short-circuit vbatt and lvb to external components and hvb to gnd. when using li_ion, short-circuit hvb to vbatt, and leave lvb open. when using ni_mh, the vb voltage is output from v_stdby in standby mode. when using li-ion, 50% of the vbat t voltage is output to v_stdby pin in standby mode. reset circuit figure 8. reset circuit block diagram when the vo1_sense or vo2_sense voltage is higher than the reference value, pgoo d1 or 2b goes high. when pgood1(int) is low and pgood1 is high, sleep(int) is forced to place the chip into the standby mode. connect a capacitor between reset1_th and pgood_delay. the capacitor is not necessary if a resistor of 330k ? or less is inserted between reset1_th and vo1_sense for reset adjustment connect the capacitor between reset1_th and pgood as directed below. when seq_select is low:between reset1_th and pgood1_delay when seq_select is high: between reset1_th and pgood2_delay use a capacitor with approxima tely half of the capacitance between pgood_delay and gnd table 8. hvb and lvb connection mode hvb lvb li_ion vbatt (27) open ni_mh gnd vbatt (27) notes 27. externally connect to vbatt. table 9. v_stdby and lswo operation input output wake(int) pgood2(int) clear v_stdby lswo l x x vbatt z h l x vbatt z h h l vo1_sense z h h h vo1_sense l z : high impedance, x : don?t care bandgap reference (pgood1 side only) pgood1, 2 reset control pgood1_delay, pgood2_delay reset1_th pgood1, 2b(int) pgood1_delay, pgood2_delay vo1_sense vo1_sense vo1_sense, vo2_sense vgate
analog integrated circuit device data freescale semiconductor 19 18730 functional device operation operational modes figure 9. reset timing diagram power supply vo1_sense, vo2_sense: ni_mh the vbatt voltage rises and is output to vin1. when pgood2(int) is high, the power switch turns on to output the vo1_sense voltage to vout1. capacitance value which is connected to vo1_sense should be higher than the capacitor connected to vout1. the vbatt voltage rises or falls and is output to vin2. when pgood2(int) is high, the power switch turns on to output the vo2_sense_in voltage to vout2. if you turn ddc2 off using the register, the power switch 2 also turns off. capacitance value which is connected to vo2_sense_in should be higher than the capacitor connected to vout2. pgood1(int) pgood1 sleep(int) table 10. output voltage of vo1_sense address: 0011 (28) b7 b6 b5 b4 b3 b2 b1 s_off_vo1_sense vo1_sense [v] (29) l l l l l l l x 1.613 l l l l l l h x 1.625 l l l l l h l x 1.638 l l l l h l l x 1.663 l l l h l l l x 1.713 l l h l l l l x 1.813 l h l l l l l x 2.013 h l l l l l l x 2.413 h l l l l l h x 2.425 h l l l l h l x 2.438 h l l l h l l x 2.463 h l l h l l l x 2.513 h l h l l l l x 2.613 h h l l l l l x 2.813 h h h h h h h x 3.200 notes 28. all combinations of input are not included. 29. operation is not guaranteed when vo1_sense input voltage is 1.8 v or lower. by connecting a diode between vin1 and vo1_sense, vin1 can output voltage higher (with the voltage difference vf) than vo1_sense.
analog integrated circuit device data 20 freescale semiconductor 18730 functional device operation operational modes power supply vo1_sense, vo2_sense: li-ion the vbatt voltage falls and is output to vo1_sense. when using li_ion, duty limit due to dmax1 is not applied to the switch. when pgood2(int) is high, the power switch turns on to output the vo 1_sense voltage to vout1. capacitance value which is connected to vo1_sense should be higher than the capacitor connected to vout1. the vbatt voltage falls using only the internal transistor and is output to vo2_sense. when using li_ion, duty limit due to dmax2 is not applied to the switch, and hg and lg are low. when pgood2(int) is high, the power switch turns on to output the vo2_sense_in voltage to vout2. if you turn ddc2 off using the register, the power switch 2 also turns off. capacitance value which is connected to vo2_sense_in should be higher than the capacitor connected to vout2. series pass power supply the series pass outputs the sregi1 voltage to srego1, the sregi2 voltage to srego2, and the sregi3 voltage to srego3. if you use mosfet as the external component in this case, connect the gate to sreg2g. table 11. output voltage of vo2_sense address: 0100 (33) b7 b6 b5 b4 b3 b2 b1 s_off_vo2_sense vo2_sense [v] l l l l l l l x 0.805 l l l l l l h x 0.811 l l l l l h l x 0.816 l l l l h l l x 0.827 l l l h l l l x 0.849 l l h l l l l x 0.893 l h l l l l l x 0.980 h l l l l l l x 1.155 h l l l l l h x 1.161 h l l l l h l x 1.166 h l l l h l l x 1.177 h l l h l l l x 1.199 h l h l l l l x 1.243 h h l l l l l x 1.330 h h h h h h h x 1.500 notes 30. all combinations of input are not included table 12. output voltage of sreg1 address: 0101 (31) b7 b6 b5 b4 b3 b2 b1 reserved sreg1 [v] (33) l l l l l l l h 0.865 l l l l l l h h 0.880 l l l l l h l h 0.895 l l l l h l l h 0.926 l l l h l l l h 0.986 l l h l l l l h 1.107
analog integrated circuit device data freescale semiconductor 21 18730 functional device operation operational modes l h l l l l l h 1.349 h l l l l l l h 1.833 h l l l l l h h 1.848 h l l l l h l h 1.863 h l l l h l l h 1.893 h l l h l l l h 1.954 h l h l l l l h 2.075 h h l l l l l h 2.317 h h h h h h h h 2.800 notes 31. all combinations of input are not included. 32. the sreg1 and 3 output voltages are determined by the combination of external resistances connected to sregc1 and 3 (65.14k ? between srego1 and sregc1, 34.86k ? between sregc1 and gnd, 73.84k ? between srego3 and sregc3, and 26.16k ? between sregc3 and gnd). table 13. output voltage of sreg2 address: 0110 (33) b7 b6 b5 b4 b3 b2 b1 b0 sreg2 [v] l l l l l l l l 0.011 l l l l l l l h 0.022 l l l l l l h l 0.033 l l l l l h l l 0.055 l l l l h l l l 0.098 l l l h l l l l 0.186 l l h l l l l l 0.361 l h l l l l l l 0.711 h l l l l l l l 1.411 h l l l l l l h 1.422 h l l l l l h l 1.433 h l l l l h l l 1.455 h l l l h l l l 1.498 h l l h l l l l 1.586 h l h l l l l l 1.761 h h l l l l l l 2.111 h h h h h h h h 2.800 notes 33. all combinations of input are not included. table 14. output voltage of sreg3 address: 0111 (34) b7 b6 b5 b4 b3 b2 cp off extg on sreg3 [v] (35) l l l l l l x x 2.080 table 12. output voltage of sreg1 address: 0101 (31) b7 b6 b5 b4 b3 b2 b1 reserved sreg1 [v] (33)
analog integrated circuit device data 22 freescale semiconductor 18730 functional device operation operational modes vg generator figure 10. circuit when using a step-up converter when wake (int) goes high from low, the start-up circuit raises the vb voltage and outputs it to vgate, then outputs the vgate voltage when pgood1 (int) goes high. the charge pump circuit can be used for both ni_mh and li_ion by setting the necessary registers. the charge pump circuit is disabled by default. the vgate voltage can be set in the range of 6 v to 4.5 v according to the combination of vgatesel1 and 2 pin connections. refer to table 16, vgate voltage settings and vgatesel1 and 2 pin connection on page 23 for the vg voltage settings. when using a charge pump, please refer to figure 11 . l l l l l h x x 2.091 l l l l h l x x 2.102 l l l h l l x x 2.125 l l h l l l x x 2.170 l h l l l l x x 2.260 h l l l l l x x 2.440 h l l l l h x x 2.451 h l l l h l x x 2.462 h l l h l l x x 2.485 h l h l l l x x 2.530 h h l l l l x x 2.620 h h h h h h x x 2.800 notes 34. all combinations of input are not included. 35. the sreg1 and 3 output voltages are determined by the combination of external resistances connected to sregc1 and 3 (65.14k ? between srego1 and sregc1, 34.86k ? between sregc1 and gnd, 73.84k ? between srego3 and sregc3, and 26.16k ? between sregc3 and gnd). table 14. output voltage of sreg3 address: 0111 (34) b7 b6 b5 b4 b3 b2 cp off extg on sreg3 [v] (35) vbatt vgate step-up pre driver swgate vbatt vgate gndgate vg_select vg_duty vgate vgate start up
analog integrated circuit device data freescale semiconductor 23 18730 functional device operation operational modes figure 11. circuit when using a charge pump table 15. vgate duty settings address : 0010 ext/int half freq rstb sleep s_off_vg vg_duty[3] vg_duty[2] vg_duty[1] vg_duty[0] duty x x x x l l l l 90 % x x x x l l l h 86 % x x x x l l h l 82 % x x x x l h l l 74 % x x x x h l l l 58 % x x x x h l l h 54 % x x x x h l h l 50 % x x x x h h l l 42 % x x x x h h h h 30 % table 16. vgate voltage settings an d vgatesel1 and 2 pin connection vgatesel1 vgatesel2 vgate [v] gnd gnd 6.0 gnd vbatt 5.5 vbatt gnd 5.0 vbatt vbatt 4.5 vgate vbatt step-up pre driver swgate start up vbatt vgate vgh cpoff vbatt vgate ch_pump gndgate vgate_select vg_duty vgate vgate
analog integrated circuit device data 24 freescale semiconductor 18730 functional device operation logic commands and registers logic commands and registers register mappings clear: clear control 1 = clear is high 0 = clear is low sleep: sleep control 1 = sleep is high 0 = sleep is low reserved: freescale defined register *1 1 = forbidden 0 = required reserved: freescale defined register *1 1 = forbidden 0 = required reserved: freescale defined register *1 1 = forbidden 0 = required reserved : freescale defined register *1 1 = forbidden 0 = required reserved : freescale defined register *1 1 = forbidden 0 = required reserved: freescale defined register *1 1 = forbidden 0 = required note: do not change reserved register from default value. *1: data write to this address (1000) is allowed for the most significant two bits only. the least significant 6 bits are only used for the factory test. when writing data, always write 0 to these six bits. psw1: vout1 power switch control 1 = power switch on 0 = power switch off psw2: vout2 power switch control 1 = power switch on 0 = power switch off pgood1: pgood1 mask *1 1 = pgood1 mask on 0 = pgood1 mask off vo2_sense: dc/dc converter channel 2 output control *2 1 = ddc2 on 0 = ddc2 off sreg1: series pass regulator channel1 output control 1 = regulator on 0 = regulator off sreg2: series pass regulator channel2 output control *3 1 = regulator off 0 = regulator on sreg3: series pass regulator channel3 output control 1 = regulator on 0 = regulator off pgood2: pgood2 mask *1 1 = pgood2 mask on 0 = pgood2 mask off *1: when switching the output voltage of vo1_sense (2), write 1 to the pgood1 (2) mask bit in advance to fix the rest output to high for preventing erroneous operation. *2: when turning ddc2 off, set the pgood2 bit to high to mask pgood2. if you turn ddc2 off, the power switch 2 also turns off. table 17. clear and sleep control register 1000 data1 data2 bit 3 2 1 0 3 2 1 0 name clear sleep reserved reserved reserved reserved reserved reserved default 0 0 0 0 0 0 0 0 table 18. power mode register 0001 data1 data2 bit 3 2 1 0 3 2 1 0 name psw1 psw2 pgood1 vout2 sreg1 sreg2 sreg3 pgood2 default 1 1 0 1 1 1 1 0
analog integrated circuit device data freescale semiconductor 25 18730 functional device operation logic commands and registers ext / int: clock select control 1 1 = external clock 0 = internal clock 2fs: clock select control 2 1 = 2fs on 0 = 2fs off rstb sleep: rstb sleep monitor *1 1 = rstb sleep monitor off 0 = rstb sleep monitor on s_off_vg: vg top side transistor off 1 = synchronous rectification off 0 = synchronous rectification on vg_duty[3]: vg duty control msb 1 = vg duty[3] is high 0 = vg duty[3] is low vg_duty[2]: vg duty control bit 2 1 = vg duty[2] is high 0 = vg duty[2] is low vg_duty[1]: vg duty control bit1 1 = vg duty[1] is high 0 = vg duty[1] is low vg_duty[0]: vg duty control lsb 1 = vg duty[0] is high 0 = vg duty[0] is low vg is controlled by pfm method. this register can change the duty by 16 steps. refer to table 15, vgate duty settings on page 23 for the correspondence between the vg duty maximum values and register settings. vo1_sense[6] : reference dac msb 1 = vo1_sense[6] on 0 = vo1_sense[6] off vo1_sense[5] : reference dac bit5 1 = vo1_sense5] on 0 = vo1_sense[5] off vo1_sense[4] : reference dac bit4 1 = vo1_sense[4] on 0 = vo1_sense[4] off vo1_sense[3] : reference dac bit3 1 = vo1_sense[3] on 0 = vo1_sense[3] off vo1_sense[2] : reference dac bit2 1 = vo1_sense[2] on 0 = vo1_sense[2] off vo1_sense[1]: refe rence dac bit1 1 = vo1_sense[1] on 0 = vo1_sense[1] off vo1_sense[0] on 0 = vo1_sense[0] off s_off_vo1_sense: ddc1 to p side (ni_mh) / bottom side (li_ion) transistor off 1 = synchronous rectification off 0 = synchronous rectification on refer to table 10, output voltage of vo1_sense on page 19 for the correspondence between the output voltage and register settings. table 19. clock select register 0010 data1 data2 bit 3 2 1 0 3 2 1 0 name ext/int half freq rstb sleep s_off_vg vg_duty [3] vg_duty[2] vg_duty[1] vg_duty[0] default 0 0 1 0 0 0 0 0 table 20. vo1_sense output voltage register 0011 data1 data2 bit 3 2 1 0 3 2 1 0 name vo1_sense [6] vo1_sense [5] vo1_sense [4] vo1_sense [3] vo1_sense [2] vo1_sense [1] vo1_sense [0] s_off_vo1_sense default 1 0 0 0 0 0 0 0
analog integrated circuit device data 26 freescale semiconductor 18730 functional device operation logic commands and registers vo2_sense[6] : reference dac msb 1 = vo2_sense[6] on 0 = vo2_sense[6] off vo2_sense[5] : reference dac bit5 1 = vo2_sense[5] on 0 = vo2_sense[5] off vo2_sense[4] : reference dac bit4 1 = vo2_sense[4] on 0 = vo2_sense[4] off vo2_sense[3] : reference dac bit3 1 = vo2_sense[3] on 0 = vo2_sense[3] off vo2_sense[2] : reference dac bit2 1 = vo2_sense[2] on 0 = vo2_sense[2] off vo2_sense[1]: refe rence dac bit1 1 = vo2_sense[1] on 0 = vo2_sense[1] off vo2_sense [0]: reference dac lsb 1 = vo2_sense [0] on 0 = vo2_sense [0] off s_off_vo2_sense: ddc2 to p side & lg (ni_mh) / bottom side (li_ion) transistor off 1 = synchronous rectification off 0 = synchronous rectification on refer to table 11, output voltage of vo2_sense on page 20 for the correspondence between the output voltage and register settings. sreg1_v[6]: refe rence dac msb 1 = sreg1_v[6] on 0 = sreg1_v[6] off sreg1_v[5]: refe rence dac bit5 1 = sreg1_v[5] on 0 = sreg1_v[5] off sreg1_v[4]: refe rence dac bit4 1 = sreg1_v[4] on 0 = sreg1_v[4] off sreg1_v[3]: refe rence dac bit3 1 = sreg1_v[3] on 0 = sreg1_v[3] off sreg1_v[2] : reference dac bit2 1 = sreg1_v[2] on 0 = sreg1_v[2] off sreg1 [1]: reference dac bit1 1 = sreg1_v[1] on 0 = sreg1_v[1] off sreg1_v[0]: reference dac lsb 1 = sreg1_v[0] on 0 = sreg1_v[0] off reserved : blank register bit (freescale pre-defined register) 1 = preferred 0 = forbidden note: do not change reserved register from default value. refer to table 12, output voltage of sreg1 on page 20 for the correspondence between the output voltage and register settings. table 21. vo2_sense output voltage register 0100 data1 data2 bit 3 2 1 0 3 2 1 0 name vo2_sense [6] vo2_sense [5] vo2_sense [4] vo2_sense [3] vo2_sense [2] vo2_sense [1] vo2_sense [0] s_off_vo2_sense default 1 0 0 0 0 0 0 0 table 22. regulator1 output voltage register 0101 data1 data2 bit 3 2 1 0 3 2 1 0 name sreg1_v[6] sreg1_v[5] sreg1_v[4] sreg1_v[3] sreg1_v[2] sreg1_v[1] sreg1_v[0] reserved default 1 1 1 1 1 1 1 1
analog integrated circuit device data freescale semiconductor 27 18730 functional device operation logic commands and registers sreg2_v[7]: refe rence dac msb 1 = sreg2_v[7] on 0 = sreg2_v[7] off sreg2_v[6]: refe rence dac bit6 1 = sreg2_v[6] on 0 = sreg2_v[6] off sreg2_v[5]: refe rence dac bit5 1 = sreg2_v[5] on 0 = sreg2_v[5] off sreg2_v[4]: refe rence dac bit4 1 = sreg2_v[4] on 0 = sreg2_v[4] off sreg2_v[3]: refe rence dac bit3 1 = sreg2_v[3] on 0 = sreg2_v[3] off sreg2_v[2]: reference dac bit2 1 = sreg2_v[2] on 0 = sreg2_v[2] off sreg2_v[1]: reference dac bit1 1 = sreg2_v[1] on 0 = sreg2_v[1] off sreg2_v[0]: reference dac lsb 1 = sreg2_v[0] on 0 = sreg2_v[0] off refer to table 13, output voltage of sreg2 on page 21 for the correspondence between the output voltage and register settings. sreg3_v[5]: refe rence dac msb 1 = sreg3_v[5] on 0 = sreg3_v[5] off sreg3_v[4]: refe rence dac bit4 1 = sreg3_v[4] on 0 = sreg3_v[4] off sreg3_v[3]: refe rence dac bit3 1 = sreg3_v[3] on 0 = sreg3_v[3] off sreg3_v[2] : reference dac bit2 1 = sreg3_v[2] on 0 = sreg3_v[2] off sreg3_v[1] : reference dac bit1 1 = sreg3_v[1] on 0 = sreg3_v[1] off sreg3_v[0]: reference dac lsb 1 = sreg3_v[0] on 0 = sreg3_v[0] off cp off: charge pump control 1 = charge pump off 0 = charge pump on extg on: vgate_ext control * 1 = vgate_ext is low (gnd level) 0 = vgate_ext is high (vg level) extg on register is assumed to use pch fet as external mosfet. if nch fet will be used, control logic should be inverted. refer to table 14, output voltage of sreg3 on page 21 for the correspondence between the output voltage and register settings. table 23. regulator2 output voltage register 0110 data1 data2 bit 3 2 1 0 3 2 1 0 name sreg2_v[7] sreg2_v[6] sreg2_v[5] sreg2_v[4] sreg2_v[3] sreg2_v[2] sreg2_v[1] sreg2_v[0] default 1 1 1 1 1 1 1 1 table 24. regulator3 output voltage register 0111 data1 data2 bit 3 2 1 0 3 2 1 0 name sreg3_v[5] sreg3_v[4] sreg3_v[3] sreg3_v[2] sreg3_v[1] sreg3_v[0] cp off extg on default 1 1 1 1 1 1 1 1
analog integrated circuit device data 28 freescale semiconductor 18730 typical applications typical applications figure 12. MPC18730 typical application diagram (ni-mh battery) vgate_ext vref vo1_sense pgnd1 vout1 sw2 vbatt vbatt lvb hvb eaout2 eain2 dmax2 vo1_sense pgood2_delay pgnd2 vin2 vo2_sense vout2 vbatt vo2_sense_in data vgate srego1 sregc1 sregc2 sregc3 vbatt gndgate sregi1 watchdog gnd seq_select ch_pump srego2 srego3 sregi3 clear bandgap vo1_sense vbatt vgate power switch1 lvb pgood1(int) pgood1(int) pgood1(int) driver reference step-updown dc/dc vmode pgood1(int) vgate power switch2 ref2 pgood2(int) vgate step-updown dc/dc pgood2(int) control v_stdby vo1_sense series pass vgate vgate vbatt vref regulator1 series pass vgate vbatt ref3 ref4 ref5 ext_clock ref1 ref2 ref3 ref4 ref5 ref dac series pass vgate regulator3 regulator2 cpoff vg_duty vg_select vgatesel1 vgatesel2 vgate vo1_sense hg lg pgood1_delay or pgood2_delay sw1 swgate on ext gate on ext_clock clear sckin wake2b wake3b wake4b srego3 pgood2 reset1_th pgood1 lswo sleep pgood1_delay buffer srego1 srego2 sreg2g control logic step-up dc/dc convertor converter reset block 2 vo1_sense reset block 1 pgood2 ch1 converter ch2 (int) vgate vo1_sense vbatt seq_select pgood1(int) eain1 eaout1 vin1 vo1_sense v_stdby vo1_sense vo1_sense vmode strb vbatt sreg12 wake1b vref dmax1 vref vref vo1_sense ref1
analog integrated circuit device data freescale semiconductor 29 18730 typical applications figure 13. MPC18730 typical application diagram (li-ion battery) vgate_ext vref dmax1 vo1_sense pgnd1 vout1 sw2 vbatt vbatt lvb hvb eaout2 eain2 dmax2 vo1_sense pgood2_delay pgnd2 vin2 vo2_sense vout2 vbatt vo2_sense_in data vgate srego1 sregc1 sregc2 sregc3 gndgate sregi1 watchdog gnd seq_select ch_pump srego2 srego3 sregi3 clear bandgap vo1_sense vbatt vgate power switch1 lvb pgood1(int) pgood1(int) pgood1(int) driver reference vo1_sense step-updown dc/dc vmode pgood1(int) vref vgate power switch2 ref2 pgood2(int) vgate step-updown dc/dc pgood2(int) control v_stdby vo1_sense series pass vgate vgate vbatt vref regulator1 series vgate vbatt ref3 ref4 ref5 ext_clock ref1 ref2 ref3 ref4 ref5 ref dac series pass vgate regulator3 regulator2 cpoff vg_duty vg_select vgatesel1 vgatesel2 vgate vo1_sense hg lg pgood1_delay or pgood2_delay sw1 swgate on ext gate on ext_clock clear sckin wake2b wake3b wake4b srego3 pgood2 reset1_th pgood1 lswo sleep pgood1_delay buffer srego1 srego2 sreg2g control logic step-up dc/dc convertor converter reset block 2 vo1_sense reset pgood2 ch1 converter ch2 vbatt vgh pass (int) vgate vo1_sense vbatt seq_select pgood1(int) eain1 eaout1 vin1 vo1_sense v_stdby vo1_sense vo1_sense vmode strb vbatt sreg12 wake1b block 1 vbatt ref1
analog integrated circuit device data 30 freescale semiconductor 18730 packaging package dimensions packaging package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the ?98a? listed below. ep (pb-free) suffix 64-pin 0.5 mm pitch plastic package 98arl10571d issue b
analog integrated circuit device data freescale semiconductor 31 18730 packaging package dimensions ep (pb-free) suffix 64-pin 0.5 mm pitch plastic package 98arl10571d issue b
analog integrated circuit device data 32 freescale semiconductor 18730 packaging package dimensions ep (pb-free) suffix 64-pin 0.5 mm pitch plastic package 98arl10571d issue b
analog integrated circuit device data freescale semiconductor 33 18730 packaging package dimensions ep (pb-free) suffix 64-pin 0.5 mm pitch plastic package 98arl10571d issue b
analog integrated circuit device data 34 freescale semiconductor 18730 revision history revision history revision date description of changes 3.0 04/2006 ? changed 34 of 64 pin names to align with application note, an3247 rev 1.0. 4.0 8/2006 ? minor changes to correct errors and inconsistencies. ? updated form and style.
MPC18730 rev. 4.0 8/2006 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the applic ation or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for us e as components in systems intended for surgical implant into the body, or other applicat ions intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indem nify and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of perso nal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2006. all rights reserved. how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com

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